1. Field of the Invention
The present invention relates to a high voltage transistor, and more particularly, to a high voltage transistor used for an electrostatic discharge protection device of an electrostatic discharge clamp circuit.
2. Description of the Prior Art
Since the irreparable damage of the integrated circuit can be caused by the electrostatic discharge (ESD), the ESD protection circuit has become a necessity to be designed into the integrated circuit, for preventing the unpredictable damage caused by the ESD during the fabrication or the usage of the integrated circuit.
The design of additionally disposing the ESD clamp circuit between power lines has been developed for effectively enhancing the ESD protection of the integrated circuit, and further effectively preventing the damage of the internal circuit by the static electricity. The conventional ESD clamp circuit is formed of LDNMOS transistors, and therefore the conventional ESD clamp circuit has an apparent snap back characteristic and a low holding voltage which is less than the supply voltage provided by the power line. Accordingly, the ESD clamp circuit will be easily mistriggered and turned on, and the latchup will be further induced. Due to the holding voltage is less than the supply voltage when the ESD clamp circuit has been turned on, the ESD clamp circuit might be operated in the holding region by the supply voltage and the high current might be further conducted. At the same time, the internal circuit is still operating, so that the internal circuit of the integrated circuit will be overheated and malfunctioned or even burned under the high current. For preventing the occurrence of the latchup, the holding voltage of the ESD clamp circuit between the power lines must be designed to be greater than the supply voltage. The design of the ESD clamp circuit nowadays is to stack multiple low voltage LDNMOS transistors to form the ESD clamp circuit. The holding voltage can be increased by stacking the transistors, so as to make the holding voltage to be greater than the supply voltage. However, the area of the ESD clamp circuit is limited by the stack of the transistors, so that the size of the chip cannot be further shrunk. Especially, the size of the chip is significantly increased with the increase of the number of the stacked transistors when the high voltage (such as 60 volts, 80 volts or 100 volts) is applied to the ESD clamp circuit. Such disadvantage is unacceptable. Moreover, the holding voltage of the LDNMOS transistor decreases as the duration of the ESD pulse becomes longer, and more transistors is then required.
As a result, providing a high voltage transistor which can be used for an ESD protection device, for enhancing the holding voltage to meet the requirement of the ESD voltage is certainly an objective in this field.